1. Field of the Invention
The invention relates to a chip package and methods for forming the same, and in particular to a chip package formed by a wafer-level packaging process.
2. Description of the Related Art
The chip packaging process is an important step in the fabrication of an electronic product. Chip packages not only protect the chips therein from outer environmental contaminants, but they also provide electrical connection paths between electronic elements inside and those outside of the chip packages.
Manufacturing processes of chip packages comprise dicing a wafer substrate into a plurality of chips. The chip is then disposed on a lead frame, whose size is greater than that of the chip. Next, conducting pads of the chip are electrically connected to bonding pads of the lead frame by gold wires so as to form external electrical connection paths of the chip.
However, using the gold wires and the lead frame as the external electrical connection paths costs a lot and increases the overall size of the chip package. As a result, it is difficult to further decrease the size of the chip package.
Thus, there exists a need in the art for development of a chip package and methods for forming the same capable of mitigating or eliminating the aforementioned problems.